1. Field of the Invention
The invention relates generally to a metal layer structure for a semiconductor device and, more particularly, to a metal layer structure of a semiconductor device for securing an alignment margin between a contact plug and a metal layer.
2. Related Technology
In a semiconductor device, a metal layer is formed as a bundle, and a lower metal layer and an upper metal layer are electrically connected with a contact plug. As the degree of integration of a device is increased, spaces between metal layers become more narrow. Meanwhile, to form a metal layer, a conductive film for a metal layer is formed, and photoresist is applied thereon. The photoresist is then patterned through a photolithography and development process using a metal mask to define a region for a metal layer to be formed. Then, the conductive film for a metal layer is etched using the photoresist pattern as an etching mask. As a result, a metal layer is formed.
For a metal layer to be connected to another lower metal layer, alignment with a contact plug has to be made. However, as the width of the metal layer and the space between metal layers becomes more narrow, the alignment margin with a contact plug is decreased and thus it is difficult to accurately align a metal layer with a contact plug. In particular, in a photolithography process of the photoresist, in the case where a mask is not aligned accurately and thus the region for a metal layer to be formed is not defined accurately, the error of an alignment with a contact plug may be produced. As a result, the contact area between the metal layer and contact plug is decreased to increase the resistance thereof, or they are not in contact with each other, resulting in a failure. In addition, one metal layer adjacent to another metal layer to be connected to a contact plug, is connected to the contact plug resulting in a failure.
In addition, current photolithography equipment is limited in its ability to overlay and thus to form a metal layer, and it is difficult to form the metal layer to be connected accurately to a lower contact plug.
In a case of a memory device, more metal layers in a core region are formed than that in a cell region, and thus it is important to ensure an alignment margin therein and further the alignment margin had to be improved in taking into consideration of a pattern size to be smaller.
FIGS. 1A and 1B are views showing conventional metal layers of a semiconductor device. A contact plug 11 is formed over a substrate on which a lower structure (not shown) such as a transistor is formed. Then, a conductive film for a metal layer is formed over the contact plug 11 and a patterning process is performed thereon to form metal layers 12a to 12c. At this time, some metal layers are connected to the contact plug 11. Here, it is an important aspect that the contact plug 11 is aligned accurately with the metal layer 12a and a predetermined space has to be formed such that the metal layer 12b or 12c, which is adjacent to the metal layer 12a, is not connected to the contact plug 11.
However, in the case where the space between the metal layers is very narrow and thus a mask is not aligned accurately in a photolithography process, the metal layer 12b or 12c, which is adjacent to the metal layer 12a to be connected to the contact plug 11, is connected to the contact plug 11 resulting in a failure. In addition, only a part of the contact plug 11 is connected to the metal layer 12a to decrease a contact surface, thereby increasing the resistance thereof.
Here, a method for widening the space between the metal layers may be proposed to solve the above drawback; however, it causes the chip size to increase, thereby reducing efficiency. In addition, in the case where an area of the contact plug 11 is decreased, it becomes difficult to align with the metal layer 12a to be connected to the contact plug 11, and in the case where an area of the contact plug 11 is increased, the space between metal layers has to be increased, which adversely affects the degree of integration.